Center for Co-design of Chip, Package, System

The Center for Co-design of Chip, Package, System conducts leading-edge research in the following areas:
   • System Architecture, Planning, Modeling and Implementation
   • IC Floor Planning, Place & Route, Design, Modeling and Characterization
   • Advanced Packaging, Substrate Fabrication, Modeling and Characterization
   • Advanced Interconnect and 3D Integration Technologies
   • Electronic Design Automation that includes Physical CAD and Multi-physics Modeling
   • Emerging Device and Interconnect Technologies

The center is organized into program specific areas where a group of faculty with complimentary expertise work on application driven technologies. An overview of the programs can be found on our research page.

Center News

CP3S Members Receive GT-ECE Roger P. Webb Awards

Congratulations to C3PS Affiliates for their recognition by the School of Electrical and Computer Engineering for their exceptional educational and mentoring skills.

Outstanding Junior Faculty Member Award: Arijit Raychowdhury, ON Semiconductor Professor, Associate Professor, School of Electrical and Computer Eng., Georgia Institute of Technology

D. Scott Wills ECE Distinguished Mentor Award: Madhavan Swaminathan, John Pippin Chair in Microsystems Packaging & Electromagnetics, Director-Center for Co-Design of Chip, Package, System (C3PS); Professor, School of Electrical and Computer Eng., Georgia Institute of Technology

The Roger P. Webb Awards Program in the School of Electrical and Computer Engineering recognizes the excellence of the School’s faculty, staff, and students and celebrates the end of the academic year. On Tuesday afternoon, April 10, 2018 from 3-5 pm at the Klaus Building Atrium, the School of ECE will honor those people who have shown exceptional dedication to their professions and studies, ECE, Georgia Tech, and the community as a whole.