Center for Co-design of Chip, Package, System

The Center for Co-design of Chip, Package, System conducts leading-edge research in the following areas:
   • System Architecture, Planning, Modeling and Implementation
   • IC Floor Planning, Place & Route, Design, Modeling and Characterization
   • Advanced Packaging, Substrate Fabrication, Modeling and Characterization
   • Advanced Interconnect and 3D Integration Technologies
   • Electronic Design Automation that includes Physical CAD and Multi-physics Modeling
   • Emerging Device and Interconnect Technologies

The center is organized into program specific areas where a group of faculty with complimentary expertise work on application driven technologies. An overview of the programs can be found on our research page.

Join the CAEML and C3PS Team in Hangzhou China for the 2017 EDAPS Symposium!
December 14 - 16, 2017

Professors Swaminathan and Franzon to present a workshop on Machine Learning for Hardware Design

Full details and registration link available here.

Center News

Raychowdhury's Research Into New Computation Paradigms Garners Best Paper Award

Arijit Raychowdhury has received the Best Paper Award from the IEEE Transactions on Mult-scale Computing Systems (TMSCS) for an article entitled "Enabling New Computation Paradigms with HyperFET.” The paper, coauthored by collaborators from Penn State, the University of Notre Dame, and the University of Pittsburgh, was published in vol. 2, iss. 1, pp. 30-48.

When augmented with traditional transistor technology (HyperFETs), phase transition devices can enable a vast class of computing primitives, from better transistors to oscillators and spike generators. Arijit and his colleagues have demonstrated through theory and experiments how HyperFETs can impact power efficiency of a class of computing architectures and applications. This work is currently being extended and explored in collaboration with Intel Corporation. 

Arijit is currently the ON Semiconductor Associate Professor of ECE and leads the Integrated Circuits and Systems Research Lab. His students and he are exploring power-efficient circuits topologies and the corresponding computing models that can enable the next generation of low-power autonomous systems.

 

Saad Bin Nasir Receives Best in Session Award at SRC TECHCON 2017

Saad Bin Nasir won the award in the Power Management track for his paper entitled, "A Reconfigurable Hybrid Low Dropout Voltage Regulator for Wide-Range Power Supply Noise Rejection and Energy-Efficiency Trade-off”. This research brings together novel control techniques and their circuit implementations in reconfigurable hybrid linear regulators for wireline and wireless IO. The principal aim of this research is to demonstrate a four-way reconfigurable linear regulator exhibiting wide range PSR and energy-efficiency trade-off. The measured power supply rejection ranges from -9dB to -34dB and corresponding power-efficiency range from 87% to 56%. Parts of this ongoing research have been previously published in the International Solid State Circuits Conference, the Journal of Solid State Circuits, the IEEE Transactions on Power Electronics, the European Solid State Circuits Conference, and IEEE Custom Integrated Circuits Conference and have gained significant traction with SRC’s member companies.