Center News

Power Delivery for Electronic Systems Consortium Upcoming Events

 

Fall 2017 Quarterly Meeting

Date: September 26, 2017
Time: 6:00 PM - 9:30 PM (EST)
Venue: Webex
Details: Members & Invited Guests only. (Registration Required)

Fall 2017 Semi-annual Meeting

Date: TBD (Expected Dates in November 2017)
Time: Day 1 - 8:00 AM to 6:00 PM, Day 2 - 8:00 AM to 1:00 PM
Venue: The Georgia Institute of Technology Atlanta Campus
Details: Members & Invited Guests only. (Registration Required)


Center for Advanced Electronics through Machine Learning Consortium (CAEML) - Upcoming Events

Workshop on Hardware Design using Machine Learning

Date: October 18, 2017
Time: 1PM to 4PM
Venue: Doubletree Hotel, San Jose CA
Details: Following the Conference on Electrical Performance of Electronic Packaging and Systems (Registration Required)

Learn how industry and academia are successfully applying statistical learning theory and machine learning algorithms to advance the state-of-the-art in electronic design automation, with emphasis on Signal Integrity, Power Integrity, and Advanced IC and Packaging Technologies. Statistical modeling techniques such as Bayesian inference, surrogate modeling, and generative modeling are used to accelerate design in a variety of application spaces, including high-speed links, power distribution, system-level ESD, IP reuse,  and place and route. The workshop speakers are affiliated with the NSF-sponsored Center for Advanced Electronics through Machine Learning. Tentatively scheduled university speakers include Elyse Rosenbaum (UIUC), Paul Franzon (NCSU), Madhavan Swaminathan (Georgia Tech) and industry speakers from Cadence, HPE, IBM, and Qualcomm.

Register for the Workshop Here.

Center News

Raychowdhury's Research Into New Computation Paradigms Garners Best Paper Award

Arijit Raychowdhury has received the Best Paper Award from the IEEE Transactions on Mult-scale Computing Systems (TMSCS) for an article entitled "Enabling New Computation Paradigms with HyperFET.” The paper, coauthored by collaborators from Penn State, the University of Notre Dame, and the University of Pittsburgh, was published in vol. 2, iss. 1, pp. 30-48.

When augmented with traditional transistor technology (HyperFETs), phase transition devices can enable a vast class of computing primitives, from better transistors to oscillators and spike generators. Arijit and his colleagues have demonstrated through theory and experiments how HyperFETs can impact power efficiency of a class of computing architectures and applications. This work is currently being extended and explored in collaboration with Intel Corporation. 

Arijit is currently the ON Semiconductor Associate Professor of ECE and leads the Integrated Circuits and Systems Research Lab. His students and he are exploring power-efficient circuits topologies and the corresponding computing models that can enable the next generation of low-power autonomous systems.

 

Saad Bin Nasir Receives Best in Session Award at SRC TECHCON 2017

Saad Bin Nasir won the award in the Power Management track for his paper entitled, "A Reconfigurable Hybrid Low Dropout Voltage Regulator for Wide-Range Power Supply Noise Rejection and Energy-Efficiency Trade-off”. This research brings together novel control techniques and their circuit implementations in reconfigurable hybrid linear regulators for wireline and wireless IO. The principal aim of this research is to demonstrate a four-way reconfigurable linear regulator exhibiting wide range PSR and energy-efficiency trade-off. The measured power supply rejection ranges from -9dB to -34dB and corresponding power-efficiency range from 87% to 56%. Parts of this ongoing research have been previously published in the International Solid State Circuits Conference, the Journal of Solid State Circuits, the IEEE Transactions on Power Electronics, the European Solid State Circuits Conference, and IEEE Custom Integrated Circuits Conference and have gained significant traction with SRC’s member companies.