JUMP: Packaging

Joint University Microelectronics Program (JUMP) Theme 3


In today’s era of big data, cloud computing, and Internet of Things devices, information is produced and shared on a scale that challenges the current processing speeds and energy load demands placed on electronics devices. These challenges are only set to expand, as the ability to create and store data increases in magnitude over the next decade.

With these computing challenges in mind, the Semiconductor Research Corporation's (SRC) Joint University Microelectronics Program (JUMP), which represents a consortium of industrial participants and the Defense Advanced Research Projects Agency (DARPA), has established a new $26 million center called the Applications and Systems-driven Center for Energy-Efficient integrated Nano Technologies (ASCENT). C3PS in partnership with the multidisciplinary, multi-university center will focus on conducting research that aims to increase the performance, efficiency and capabilities of future computing systems for both commercial and defense applications. By going beyond current industry approaches, such as two dimensional scaling and the addition of performance boosters to complementary metal oxide semiconductors, or CMOS technology, the GT team will seek to provide enhanced performance and energy consumption at lower costs.


Current approaches towards integrating computing resources (logic and memory) include 2.5D and 3D approaches. Although they do provide scalability beyond Moore’s Law, they are limited by technology choices, number of layers in the integrated stack and lack of compatibility with integrated RF or power conversion. To enable RF components, passives and power converters, a System-on-package (SoP) approach has been proposed, but they suffer from (a) low number of die to die interconnects, (b) low bandwidth between chips (in the order of 10Gbps), (c) inefficient power delivery and management (since the output of the DC-DC converter is routed at 1-2.5V via a power plane thereby incurring I2R losses), (d) lack of testability because the entire SoP needs to be tested simultaneously on the package thus compromising yield and loss of good dies that fail at the system level because of faulty passives or other dies. This results in significant technological challenges in enabling the next generations of heterogeneous integration where monolithic vertical CMOS technologies, spin-based technologies, high-speed RF components and switches along with integrated power conversion and distribution are connected in a unified high-density, energy-efficient fabric. Our goal is address these critical challenges in the state-of-the art technologies through synergistic innovations at material, devices, circuits, systems and tool chain development. C3PS plans to expand its current center capabilities through JUMP in areas related to power delivery, machine learning, multi-physics simulation and system design that includes new circuit architectures, power converters, magnetic materials, high frequency components, vertically integrated tools and other platform technologies on a common interconnect fabric.


Madhavan Swaminathan(Theme 3 Lead) Muhannad Bakir


•Claudio Alvarez •Osama Waqar Bhatti •Venkatesh Avula •Kai Qi Huang •Serhat Erdogan •William Wahby

Collaborating Universities

•University of California, Santa Barbara (UCSB) •Purdue University •University of California, Los Angeles (UCLA) •Stanford University •Cornell University •University of Notredame   


Semiconductor Research Corporation •DARPA •Several member companies